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DS90CF564 - LVDS

This page provides the datasheet information for the DS90CF564, a member of the DS90CF563 LVDS family.

Datasheet Summary

Description

The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Features

  • 1.
  • 2 20 to 65 MHz Shift Clk Support.
  • Up to 171 Mbytes/s Bandwidth.
  • Cable Size is Reduced to Save Cost.
  • 290 mV Swing LVDS Devices for Low EMI.
  • Low Power CMOS Design (< 550 mW typ).
  • Power-down Mode Saves Power (< 0.25 mW).
  • PLL Requires No External Components.
  • Low Profile 48-Lead TSSOP Package.
  • Falling Edge Data Strobe.
  • Compatible with TIA/EIA-644 LVDS Standard.
  • Single Pixel Per Clock XGA (1024 x 768).

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Other Datasheets by Texas Instruments

Full PDF Text Transcription

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DS90CF563, DS90CF564 www.ti.com SNLS107E – JULY 1997 – REVISED APRIL 2013 DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF563, DS90CF564 FEATURES 1 •2 20 to 65 MHz Shift Clk Support • Up to 171 Mbytes/s Bandwidth • Cable Size is Reduced to Save Cost • 290 mV Swing LVDS Devices for Low EMI • Low Power CMOS Design (< 550 mW typ) • Power-down Mode Saves Power (< 0.25 mW) • PLL Requires No External Components • Low Profile 48-Lead TSSOP Package • Falling Edge Data Strobe • Compatible with TIA/EIA-644 LVDS Standard • Single Pixel Per Clock XGA (1024 x 768) • Supports VGA, SVGA, XGA and Higher • 1.
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