DS90CF564 Overview
The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted.
DS90CF564 Key Features
- 2 20 to 65 MHz Shift Clk Support
- Up to 171 Mbytes/s Bandwidth
- Cable Size is Reduced to Save Cost
- 290 mV Swing LVDS Devices for Low EMI
- Low Power CMOS Design (< 550 mW typ)
- Power-down Mode Saves Power (< 0.25 mW)
- PLL Requires No External ponents
- Low Profile 48-Lead TSSOP Package
- Falling Edge Data Strobe
- patible with TIA/EIA-644 LVDS Standard
