DS90CR484 Datasheet | Texas Instruments

DS90CR483, DS90CR484 .ti. SNLS047H - FEBRUARY 2000 - REVISED APRIL 2013 DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz Check for Samples: DS90CR483, DS90CR484 Features - 2 Up to 5.38 Gbits/sec Bandwidth - 33 MHz to 112 MHz Input Clock Support - LVDS SER/DES Reduces Cable and connector Size - Pre-Emphasis Reduces Cable Loading Effects - DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion - Cable Deskew of +/- 1 LVDS Data Bit Time (up to 80 MHz Clock Rate) - 5V Tolerant Tx IN and Control Input Pins - Flow Through Pinout for Easy PCB Design - +3.3V Supply Voltage - Transmitter Rejects Cycle-to-Cycle Jitter - Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard - Both Devices are Available in 100 Lead TQFP Package DESCRIPTION The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled and transmitted. The DS90CR484 receiver converts the LVDS data streams back into 48 bits of CMOS/TTL data. At a transmit clock frequency of 112MHz, 48 bits of TTL data are transmitted at a rate of 672Mbps per LVDS data channel. Using a 112MHz clock, the data throughput is 5.38Gbit/s (672Mbytes/s). The multiplexing of data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form...