DS90CR484A Overview
The DS90CR483A transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled and transmitted.
DS90CR484A Key Features
- 2 Up to 5.38 Gbits/sec Bandwidth
- 33 MHz to 112 MHz Input Clock Support
- LVDS SER/DES Reduces Cable and Connector Size
- Pre-emphasis Reduces Cable Loading Effects
- DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion
- Cable Deskew of +/-1 LVDS Data Bit Time (up to 80 MHz Clock Rate)
- 5V Tolerant TxIN and Control Input Pins
- Flow Through Pinout for Easy PCB Design
- +3.3V Supply Voltage
- Transmitter Rejects Cycle-to-Cycle Jitter
