Datasheet4U Logo Datasheet4U.com

DS92LV040A - 4-Channel Bus LVDS Transceiver

General Description

The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces.

The device operates from a single 3.3-V power supply and includes four differential line drivers and four receivers.

Key Features

  • 1 Bus LVDS Signaling.
  • Propagation Delay: Driver 2.3 ns Max, Receiver 3.2 ns Max.
  • Low power CMOS Design.
  • 100% Transition Time 1 ns Driver Typical, 1.3 ns Receiver Typical.
  • High Signaling Rate Capability (above 155 Mbps).
  • 0.1 V to 2.3 V Common Mode Range for VID = 200 mV.
  • 70 mV Receiver Sensitivity.
  • Supports Open and Terminated Failsafe on Port Pins.
  • 3.3-V Operation.
  • Glitch Free Power up/down (Driver & Receiv.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DS92LV040A 4 Channel Bus LVDS Transceiver National Semiconductor
DS92LV0411 5 - 50 MHz Channel Link II Serializer/Deserializer National Semiconductor
DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer National Semiconductor
DS92LV0421 10 - 75 MHz Channel Link II Serializer/Deserializer National Semiconductor
DS92LV0422 10 - 75 MHz Channel Link II Serializer/Deserializer National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
DS92LV0411 Link-II Serializer/Deserializer
DS92LV0412 Link-II Serializer/Deserializer
DS92LV0421 10-MHz to-75 MHz Channel Link-II Serializer/Deserializer
DS92LV0422 10-MHz to-75 MHz Channel Link-II Serializer/Deserializer
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Product Folder Order Now Technical Documents Tools & Software Support & Community DS92LV040A SNOS521E – JANUARY 2001 – REVISED JANUARY 2018 DS92LV040A 4 Channel Bus LVDS Transceiver 1 Features •1 Bus LVDS Signaling • Propagation Delay: Driver 2.3 ns Max, Receiver 3.2 ns Max • Low power CMOS Design • 100% Transition Time 1 ns Driver Typical, 1.3 ns Receiver Typical • High Signaling Rate Capability (above 155 Mbps) • 0.1 V to 2.3 V Common Mode Range for VID = 200 mV • 70 mV Receiver Sensitivity • Supports Open and Terminated Failsafe on Port Pins • 3.