Datasheet4U Logo Datasheet4U.com

LM98620 - 10-Bit 70 MSPS 6 Channel Imaging Signal Processor

General Description

The LM98620 is a fully integrated, 10-Bit, 70 MSPS signal processing solution for high performance digital color copiers, scanners, and other image processing applications.

Key Features

  • 1 3.3 V Single Supply Operation.
  • CDS or S/H Processing.
  • 35 MHz Channel Rate.
  • Enhanced ESD Protection on Timing, Control and LVDS Pins.
  • Low Power CMOS Design.
  • 12 Terminal to 16 Terminal (Selectable) LVDS Serialized Data Output.
  • 4-Wire Serial Interface.
  • 2 Channel Symmetrical Architecture.
  • Independent Gain and Offset Correction for Each Channel.
  • Digital Black Level Calibration for Each Channel.
  • Digita.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
LM98640QML 40 MSPS Analog Front-End National Semiconductor Corporation
LM9800 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor National Semiconductor
LM9801 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor National Semiconductor
LM9810 10/12-Bit Image Sensor Processor Analog Front-End National Semiconductor
LM9811 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
LM98640 Analog Front-End
LM98640QML-SP 40-MSPS Analog Front-End
LM98519 10-bit 65 MSPS 6 Channel Imaging Signal Processor
LM98555 CCD Driver
LM98714 45 MSPS Analog Front-End

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LM98620 SNAS426C – FEBRUARY 2008 – REVISED MAY 2014 LM98620 10-Bit 70 MSPS 6 Channel Imaging Signal Processor with LVDS Output 1 Features •1 3.3 V Single Supply Operation • CDS or S/H Processing • 35 MHz Channel Rate • Enhanced ESD Protection on Timing, Control and LVDS Pins • Low Power CMOS Design • 12 Terminal to 16 Terminal (Selectable) LVDS Serialized Data Output • 4-Wire Serial Interface • 2 Channel Symmetrical Architecture • Independent Gain and Offset Correction for Each Channel • Digital Black Level Calibration for Each Channel • Digital White Level Calibration for Each Channel • Programmable Input Clamp • Key Specifications – Maximum Input Level: – 1.2 Vp-p (CDS Gain = 1.0) – 0.