LMK03001 Datasheet | Texas Instruments

URES - Integrated VCO with Very Low Phase Noise Floor - Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 d Bc/Hz - VCO Divider Values of 2 to 8 (All Divides) - Channel Divider Values of 1, 2 to 510 (even divides) - LVDS and LVPECL Clock Outputs - Partially Integrated Loop Filter - Dedicated Divider and Delay Blocks on Each Clock Output - Pin patible Family of Clocking Devices - 3.15 to 3.45 V Operation - Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm) - 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a Clean Input Clock 1.1 TARGET APPLICATIONS - Data Converter Clocking - Networking, SONET/SDH, DSLAM - Wireless Infrastructure - Medical - Test and Measurement - Military / Aerospace Device LMK03000C LMK03000 LMK03000D LMK03001C LMK03001 LMK03001D LMK03033C LMK03033 Outputs 3 LVDS 5 LVPECL 4 LVDS 4 LVPECL Tuning Range RMS Jitter (MHz) (fs) -...