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LMK04610 - Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner

Description

The LMK0461x device family is the industry's highest performance and lowest power jitter cleaner with JESD204B support.

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Features

  • 1 Dual-loop PLL architecture.
  • Ultra low noise (10 kHz to 20 MHz):.
  • 48-fs RMS jitter at 1966.08 MHz.
  • 50-fs RMS jitter at 983.04 MHz.
  • 61-fs RMS jitter at 122.88 MHz.
  • 165-dBc/Hz noise floor at 122.88 MHz.
  • JESD204B support.
  • Single shot, pulsed, and continuous SYSREF.
  • 10 differential output clocks in 8 frequency groups.
  • Programmable output swing between 700 mVpp to 1600 mVpp.
  • Each output pair c.

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Datasheet preview – LMK04610

Datasheet Details

Part number LMK04610
Manufacturer Texas Instruments
File Size 2.50 MB
Description Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner
Datasheet download datasheet LMK04610 Datasheet
Additional preview pages of the LMK04610 datasheet.

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Full PDF Text Transcription

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Product Folder Order Now Technical Documents Tools & Software Support & Community LMK04610 SNAS699B – JANUARY 2017 – REVISED JULY 2019 LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs 1 Features •1 Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.
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