LMK04616 Overview
The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO.
LMK04616 Key Features
- 1 Dual-loop PLL architecture
- Ultra low noise (10 kHz to 20 MHz)
- 48-fs RMS jitter at 1966.08 MHz
- 50-fs RMS jitter at 983.04 MHz
- 61-fs RMS jitter at 122.88 MHz
- 165-dBc/Hz noise floor at 122.88 MHz
- JESD204B support
- Single shot, pulsed, and continuous SYSREF
- 16 differential output clocks in 8 frequency groups
- Programmable output swing between 700