LMK04821 Overview
Key Specifications
Package: Module
Description
The LMK0482x family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks.
Key Features
- 1 JEDEC JESD204B Support
- Ultra-Low RMS Jitter – 88 fs RMS Jitter (12 kHz to 20 MHz) – 91 fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at 245.76 MHz
- Up to 1 Buffered VCXO/Crystal Output from PLL1 – LVPECL, LVDS, 2xLVCMOS Programmable
- Dual Loop PLLatinum™ PLL Architecture
- 50% Duty Cycle Output Divides, 1 to 32 (even and odd)
