LMK04828 - Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

This page provides the datasheet information for the LMK04828, a member of the LMK04821 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner family.

Product Overview

Texas Instruments

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Datasheet Details

Part number	LMK04828
Manufacturer	Texas Instruments
File Size	4.43 MB
Description	Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
Datasheet	LMK04828 Datasheet
Additional preview pages of the LMK04828 datasheet.

LMK04828 Product details

Description

The LMK0482x family is the industry's highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks.

SYSREF can be provided using both DC and AC coupling.

Features

1 JEDEC JESD204B Support.
Ultra-Low RMS Jitter.
88 fs RMS Jitter (12 kHz to 20 MHz).
91 fs RMS Jitter (100 Hz to 20 MHz).
162.5 dBc/Hz Noise Floor at 245.76 MHz.
Up to 14 Differential Device Clocks from PLL2.
Up to 7 SYSREF Clocks.
Maximum Clock Output Frequency 3.1 GHz.
LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2.
Up to 1 Buffered VCXO/Crystal Output from PLL1.
LVPECL, LVDS,.

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Published: Jul 2, 2023 |