OMAPL137-HT
Overview
- Highlights - Bit-Field Extract, Set, Clear - Dual Core SoC - Normalization, Saturation, Bit-Counting
- 300-MHz ARM926EJ-S™ RISC MPU - Compact 16-Bit Instructions
- 300-MHz C674x™ VLIW DSP
- C674x Two Level Cache Memory Architecture - TMS320C674x Fixed/Floating-Point VLIW - 32K-Byte L1P Program RAM/Cache DSP Core - 32K-Byte L1D Data RAM/Cache - Enhanced Direct-Memory-Access Controller - 256K-Byte L2 Unified Mapped RAM/Cache 3 (EDMA3) - Flexible RAM/Cache Partition (L1 and L2) - 128K-Byte RAM Shared Memory - 1024KB L2 ROM - Two External Memory Interfaces
- Enhanced Direct-Memory-Access Controller 3 - Two External Memory Interfaces Modules (EDMA3): - LCD Controller - 2 Transfer Controllers - Two Serial Peripheral Interfaces (SPI) - 32 Independent DMA Channels - Multimedia Card (MMC)/Secure Digital (SD) - 8 Quick DMA Channels - Two Master/Slave Inter-Integrated Circuit - Programmable Transfer Burst Size - One Host-Port Interface (HPI)
- TMS320C674x™ Fixed/Floating-Point VLIW DSP - USB 1.1 OHCI (Host) With Integrated PHY Core (USB1) - Load-Store Architecture With Non-Aligned
