Datasheet Summary
.ti.
SPRS815C
- DECEMBER 2011
- REVISED APRIL 2013
OMAPL138B C6-Integra™ DSP+ARM® Processor
Check for Samples: OMAPL138B-EP
1 OMAPL138B C6-Integra™ DSP+ARM® Processor
1.1 Features
- Highlights
- C674x Two Level Cache Memory Architecture
- Dual Core SoC
- 32K-Byte L1P Program RAM/Cache
- 345-MHz ARM926EJ-S™ RISC MPU
- 32K-Byte L1D Data RAM/Cache
- 345-MHz C674x Fixed/Floating-Point VLIW
- 256K-Byte L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
- Supports TI’s Basic Secure Boot
- Enhanced Direct-Memory-Access Controller 3
- Enhanced Direct-Memory-Access Controller
(EDMA3):
(EDMA3)
- 2 Channel Controllers
- Serial ATA...