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PLL1707-Q1 - 3.3-V DUAL-PLL MULTICLOCK GENERATOR

General Description

The PLL1707 is a low-cost phase-locked loop (PLL) multiclock generator.

The PLL1707 can generate four system clocks from a 27-MHz reference input frequency.

The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins.

Key Features

  • 1.
  • Qualified for Automotive.

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Full PDF Text Transcription (Reference)

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PLL1707-Q1 www.ti.com SLES259A – JUNE 2010 – REVISED MARCH 2011 3.3-V DUAL-PLL MULTICLOCK GENERATOR Check for Samples: PLL1707-Q1 FEATURES 1 • Qualified for Automotive Applications • 27-MHz Master Clock Input • Generated Audio System Clock – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) • Zero PPM Error Output Clocks • Low Clock Jitter: 50 ps (Typical) • Multiple Sampling Frequencies: fS = 32, 44.1, 48, 64, 88.2, 96 kHz • 3.