SN54ABT16241A Datasheet | Texas Instruments

D Members of the Texas Instruments Widebus™ Family D State-of-the-Art EPIC-ΙΙB™ Bi CMOS Design Significantly Reduces Power Dissipation D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D Flow-Through Architecture Optimizes PCB Layout D High-Drive Outputs (- 32-m A IOH, 64-m A IOL) D Latch-Up Performance Exceeds 500 m A Per JESD 17 D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) D Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings description The ’ABT16241A devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. SN54ABT16241A, SN74ABT16241A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS096G - FEBRUARY 1991 - REVISED OCTOBER 1998 SN54ABT16241A . . . WD PACKAGE SN74ABT16241A . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4OE 24 48 2OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3 32 3A4 31 VCC 30 4A1 29 4A2 28 GND 27 4A3 26 4A4 25 3OE These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and plementary output-enable (OE and OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE should be tied to GND through a pulldown resistor; the...