Datasheet4U Logo Datasheet4U.com

SN54ABT162841 - 20-BIT BUS-INTERFACE D-TYPE LATCHES

Description

These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.

📥 Download Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
D Members of the Texas Instruments WidebusE Family D Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D Ioff and Power-Up 3-State Support Hot Insertion D Distributed VCC and GND Pins Minimize High-Speed Switching Noise D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 description/ordering information These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
Published: |