SN54ABT657A
SN54ABT657A is OCTAL TRANSCEIVERS manufactured by Texas Instruments.
description
The 'ABT657A transceivers have eight noninverting buffers with parity-generator/ checker circuits and control signals. The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.
B5
4 3 2 1 28 27 26
ODD/EVEN 5
25 A3
ERR 6
24 A2
PARITY 7
23 A1
NC 8
22 NC
B8 9
21 T/R
B7 10
20 OE
B6 11
19 B1
12 13 14 15 16 17 18
B4
B3
B2
Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.
- No internal connection
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is low, indicating a parity error.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas...
