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D Members of the Texas Instruments
Widebus™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown Resistors
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages
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