SN54AC533 Datasheet | Texas Instruments

description /ordering information The ’AC533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the plements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 4Q SN54AC533 . . . J OR W PACKAGE SN74AC533 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) OE 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 LE SN54AC533 . . . FK PACKAGE (TOP VIEW) 8Q 1Q 1D 3 2 1 20 19 2D 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 9 10 11 12 13 5Q 5D To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP -...