Datasheet4U Logo Datasheet4U.com

SN54AC533 - OCTAL TRANSPARENT D-TYPE LATCHES

Description

The ’AC533 devices are octal transparent D-type latches with 3-state outputs.

When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs.

📥 Download Datasheet

📁 Similar Datasheet

  • SN54HC595J - 16-bit bus transceiver and transparant D-type latch (nexperia)
  • SN54LS00 - QUAD 2-INPUT NAND GATE (Motorola Inc)
  • SN54LS01 - QUAD 2-INPUT NAND GATE (Motorola Inc)
  • SN54LS02 - QUAD 2-INPUT NOR GATE (Motorola Inc)
  • SN54LS03 - QUAD 2-INPUT NAND GATE (Motorola Inc)
  • SN54LS04 - HEX INVERTER (Motorola Inc)
  • SN54LS05 - HEX INVERTER (Motorola Inc)
  • SN54LS08 - QUAD 2-INPUT AND GATE (Motorola Inc)
  • SN54LS09 - QUAD 2-INPUT AND GATE (Motorola Inc)
  • SN54LS10 - TRIPLE 3-INPUT NAND GATE (Motorola Inc)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
SN54AC533, SN74AC533 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10.5 ns at 5 V D 3-State Inverting Outputs Drive Bus Lines Directly D Full Parallel Access for Loading description/ordering information The ’AC533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state.
Published: |