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SN65EPT22 - 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer

General Description

The SN65EPT22 is a low power dual LVTTL to LVPECL translator device.

The device includes circuitry to maintain known logic HIGH level when inputs are in open condition.

The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.

Key Features

  • 1 Dual 3.3V LVTTL to LVPECL Buffer.
  • Operating Range.
  • LVPECL VCC = 3.0 V to 3.6 V With GND = 0 V.
  • Support for Clock Frequencies to 2.0 GHz (typ).
  • 420 ps Typical Propagation Delay.
  • Deterministic HIGH Output Value for Open Input Conditions.
  • Built-in Temperature Compensation.
  • Drop in Compatible to MC100ELT23.
  • PNP Single Ended Inputs for Minimal Loading 3.

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Full PDF Text Transcription for SN65EPT22 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SN65EPT22. For precise diagrams, and layout, please refer to the original PDF.

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN65EPT22 SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014 SN65EPT22 3.3 V Dual LVTTL...

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26B – DECEMBER 2008 – REVISED NOVEMBER 2014 SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer 1 Features •1 Dual 3.3V LVTTL to LVPECL Buffer • Operating Range – LVPECL VCC = 3.0 V to 3.6 V With GND = 0 V • Support for Clock Frequencies to 2.0 GHz (typ) • 420 ps Typical Propagation Delay • Deterministic HIGH Output Value for Open Input Conditions • Built-in Temperature Compensation • Drop in Compatible to MC100ELT23 • PNP Single Ended Inputs for Minimal Loading 3 Description The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level whe

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