SN65LV1021 Datasheet | Texas Instruments

FEATURES - 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock - Pin-patible Superset of NSM DS92LV1021/DS92LV1212 - Chipset (Serializer/Deserializer) Power Consumption <350 m W (Typ) at 40 MHz - Synchronization Mode for Faster Lock - Lock Indicator - No External ponents Required for PLL - Low-Cost 28-Pin SSOP Package - Industrial Temperature Qualified, TA = -40°C to 85°C - Programmable Edge Trigger on Clock (Rising or Falling Edge) - Flow-Through Pinout for Easy PCB Layout SYNC1 SYNC2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 TCLK_R/F TCLK SN65LV1021...