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SN65LV1021 - 10:1 LVDS SERIALIZER/DESERIALIZER

General Description

The SN65LV1021 serializer and SN65LV1212 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 40 MHz.

Key Features

  • 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock.
  • Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212.
  • Chipset (Serializer/Deserializer) Power Consumption.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SN65LV1021 SN65LV1212 www.ti.