SN65LVDS17 Overview
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17. The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC),...
SN65LVDS17 Key Features
- Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
- Clock Rates to 2 GHz
- 140-ps Output Transition Times
- 0.11 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
- 2.5-V or 3.3-V Supply Operation
- 2-mm × 2-mm Small-Outline No-Lead Package
SN65LVDS17 Applications
- PECL-to-LVDS Translation