SN65LVDS3486B Datasheet | Texas Instruments

.ti. SN65LVDS32B, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B SLLS440B - OCTOBER 2000 - REVISED APRIL 2007 HIGH-SPEED DIFFERENTIAL RECEIVERS Features - Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates (1) up to 400 Mbps - Operates With a Single 3.3-V Supply - - 2-V to 4.4-V mon-Mode Input Voltage Range - Differential Input Thresholds <50 m V With 50 m V of Hysteresis Over Entire mon Mode Input Voltage Range - Integrated 110-Ω Line Termination Resistors Offered With the LVDT Series - Propagation Delay Times 4 ns (typ) - Active Fail Safe Assures a High-Level Output With No Input - Bus-Pin ESD Protection Exceeds 15 k V HBM - Inputs Remain High-Impedance on Power Down - Remended Maximum Parallel Rate of 200 M-Transfer/s - Available in Small-Outline Package With 1,27-mm Terminal Pitch - Pin-patible With the AM26LS32, MC3486, or µA9637 DESCRIPTION This family of differential line receivers offers improved performance and Features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers. D PACKAGE (TOP VIEW) SN65LVDS32B SN65LVDT32B Logic Diagram (positive logic) 1B 1 1A 2 16 VCC 15...