SN65LVDS3486A Datasheet | Texas Instruments

SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A HIGH-SPEED DIFFERENTIAL RECEIVERS SLLS368C - JULY 1999 - REVISED JANUARY 2000 D Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates† Up to 400 Mbps D Operates With a Single 3.3 V Supply D - 2 V to 4.4 V mon-Mode Input Voltage Range D Differential Input Thresholds <50 m V With 50 m V of Hysteresis Over Entire mon-Mode Input Voltage Range D Integrated 110Ω Line Termination Resistors Offered With the LVDT Series D Propagation Delay Times 4 ns (typ) D Open-Circuit and Terminated Fail Safe Assures a High-Level Output With No Input D Bus-Pin ESD Protection Exceeds 15 k V D Outputs High-Impedance With VCC < 1.5 V D Power Dissipation <400 m W With Four Receivers Switching at 200 MHz D Available in Small-Outline Package With 1,27 mm Terminal Pitch D Pin-patible With the AM26LS32, MC3486, or u A9637 description This family of differential line receivers offer improved performance and Features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard providing a better overall solution for the cabled environment. The next generation family of products is an extension to TI’s overall product portfolio and is not necessarily a replacement for older LVDS receivers. Improved Features include an input monmode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. SN65LVDS32A SN65LVDT32A D PACKAGE (TOP VIEW) Logic Diagram (positive logic) 1B 1 1A 2 16 VCC 15...