SN65LVDS34 Datasheet | Texas Instruments

.ti. SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS Check for Samples: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 Features - 400-Mbps Signaling Rate(1) and 200-Mxfr/s Data Transfer Rate - Operates With a Single 3.3-V Supply - -4 V to 5 V mon-Mode Input Voltage Range - Differential Input Thresholds <±50 m V With 50 m V of Hysteresis Over Entire mon-Mode Input Voltage Range - Integrated 110-Ω Line Termination Resistors On LVDT Products - TSSOP Packaging (33 Only) - plies With TIA/EIA-644 (LVDS) - Active Failsafe Assures a High-Level Output With No Input - Bus-Pin ESD Protection Exceeds 15 k V HBM - Input Remains High-Impedance on Power Down - TTL Inputs Are 5 V Tolerant - Pin-patible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B (1) The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second). DESCRIPTION This family of four LVDS data line receivers offers the widest mon-mode input voltage range in the industry. These receivers provide an input voltage range specification patible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option. Precise control of the differential input voltage thresholds allows for inclusion of 50 m V of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 m V over the full input mon-mode voltage range. The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits. SN65LV...