SN65LVDS93 Overview
Key Specifications
Package: TSSOP
Pins: 56
Operating Voltage: 3.3 V
Max Voltage (typical range): 3.6 V
Description
The SN65LVDS93 LVDS serdes (serializer/ deserializer) transmitter contains four 7-bit parallelload serial-out shift registers, a 7נclock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94.
Key Features
- 28:4 Data Channel Compression at up to 1.904 Gigabits per Second Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential
- Selectable Rising or Falling Clock Edge Triggered Inputs
- Bus Pins Tolerate 6-kV HBM ESD
