SN65LVDS95 Overview
Key Specifications
Package: TSSOP
Pins: 48
Operating Voltage: 3.3 V
Max Voltage (typical range): 3.6 V
Description
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.
Key Features
- 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant Data Inputs
