SN65LVDS95 Description
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a patible receiver, such as the...
SN65LVDS95 Key Features
- 3:21 Data Channel pression at up to 1.428 Gigabits/s Throughput
- Suited for Point-to-Point Subsystem munication With Very Low EMI
- 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant Data Inputs
- 'LVDS95 Has Rising Clock Edge Triggered
- Bus Pins Tolerate 6-kV HBM ESD
- Packaged in Thin Shrink Small-Outline
- Consumes <1 mW When Disabled
- Wide Phase-Lock Input Frequency Range