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SN65LVDS95 - LVDS SERDES TRANSMITTER

Description

The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit.

Features

  • 1.
  • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput.
  • Suited for Point-to-Point Subsystem Communication With Very Low EMI.
  • 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential.
  • Operates From a Single 3.3-V Supply and 250 mW (Typ).
  • 5-V Tolerant Data Inputs.
  • 'LVDS95 Has Rising Clock Edge Triggered Inputs.
  • Bus Pins Tolerate 6-kV HBM ESD.
  • Packaged in Thin Shr.

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Datasheet preview – SN65LVDS95

Datasheet Details

Part number SN65LVDS95
Manufacturer Texas Instruments
File Size 473.23 KB
Description LVDS SERDES TRANSMITTER
Datasheet download datasheet SN65LVDS95 Datasheet
Additional preview pages of the SN65LVDS95 datasheet.

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Full PDF Text Transcription

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SN65LVDS95 www.ti.com LVDS SERDES TRANSMITTER Check for Samples: SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY 2011 FEATURES 1 • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput • Suited for Point-to-Point Subsystem Communication With Very Low EMI • 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential • Operates From a Single 3.
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