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SN65LVDS95 Datasheet LVDS SERDES TRANSMITTER

Manufacturer: Texas Instruments

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General Description

The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit.

These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.

When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising edge of the input clock signal (CLKIN).

Overview

SN65LVDS95 www.ti.com LVDS SERDES TRANSMITTER Check for Samples: SN65LVDS95 SLLS297J – MAY 1998 – REVISED MAY.

Key Features

  • 1.
  • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput.
  • Suited for Point-to-Point Subsystem Communication With Very Low EMI.
  • 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential.
  • Operates From a Single 3.3-V Supply and 250 mW (Typ).
  • 5-V Tolerant Data Inputs.
  • 'LVDS95 Has Rising Clock Edge Triggered Inputs.
  • Bus Pins Tolerate 6-kV HBM ESD.
  • Packaged in Thin Shr.

More Datasheets from Texas Instruments

Part Number Description
SN65LVDS95-EP LVDS SERDES TRANSMITTER
SN65LVDS95-Q1 LVDS SERDES TRANSMITTER
SN65LVDS93 LVDS SERDES TRANSMITTER
SN65LVDS93A TRANSMITTER
SN65LVDS93A-Q1 TRANSMITTER
SN65LVDS94 LVDS SERDES RECEIVER
SN65LVDS96 LVDS SERDES RECEIVER
SN65LVDS9637 High-Speed Differential Line Receivers
SN65LVDS9637A HIGH-SPEED DIFFERENTIAL RECEIVERS
SN65LVDS9637B HIGH-SPEED DIFFERENTIAL RECEIVERS