SN65LVDS96 Overview
Key Specifications
Package: TSSOP
Pins: 48
Operating Voltage: 3.3 V
Max Voltage (typical range): 3.6 V
Description
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous data at a lower transfer rate.
Key Features
- 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant SHTDN Input
