SN74ABT373 Datasheet | Texas Instruments

description The eight latches of the ’ABT373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. 4Q SN54ABT373 . . . FK PACKAGE (TOP VIEW) 8Q 1Q 1D 2D 3 2 1 20 19 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 9 10 11 12 13 5Q 5D OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT373 is characterized for operation over the full military temperature range of - 55°C to 125°C. The SN74ABT373 is characterized for operation from - 40°C to 85°C. FUNCTION TABLE (each latch) INPUTS OE LE OUTPUT...