SN74ABT5402A Datasheet | Texas Instruments

description These 12-bit buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. SN54ABT5402A . . . JT PACKAGE SN74ABT5402A . . . DW PACKAGE (TOP VIEW) Y1 1 Y2 2 Y3 3 Y4 4 Y5 5 Y6 6 GND 7 Y7 8 Y8 9 Y9 10 Y10 11 Y11 12 Y12 13 OE1 14 28 D1 27 D2 26 D3 25 D4 24 D5 23 D6 22 D7 21 VCC 20 D8 19 D9 18 D10 17 D11 16 D12 15 OE2 SN54ABT5402A . . . FK PACKAGE (TOP VIEW) D9 D8 D7 D6 D5 D4 The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all 12 outputs are in the high-impedance state. The outputs, which are designed to source or sink up to 12 m A, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Y5 Y6 Y7 4 3 2 1 28 27 26 D3 5 25 D10 D2 6 24 D11 D1 7 23 D12 Y1 8 22 OE2 Y2 9 21 OE1 Y3 10 20 Y12 Y4 11 19 Y11 12 13 14 15 16 17...