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SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
D Members of the Texas Instruments
Widebus ™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Bus Hold on Data Inputs Eliminates the
Need for Ext
SN74ABTH16260 Datasheet
