SN74ACT1071D Datasheet | Texas Instruments

description This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1071 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state. The SN74ACT1071 is characterized for operation from - 40°C to 85°C. logic diagram, one of ten channels (positive logic) D1 1 VCC 11 VCC 10 GND 3 4 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 4- 1 SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 - D3994, MARCH 1992 - REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC - - - - - - - - - - - . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) - - - - - - - - . - 0.5 V to VCC + 0.5 V Continuous input clamp current, IIK (VI < 0 or VI > VCC) - - - - - - - . ± 20 m A Positive-peak input clamp current, IIK (VI > VCC) (tw < 1 µs, duty cycle < 20%) - - ....