SN74AHCT126-EP Datasheet | Texas Instruments

he SN74AHCT126 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 125°C SOIC - D TSSOP - PW Tape and reel Tape and reel SN74AHCT126QDREP SN74AHCT126QPWREP AHCT126QEP HB126EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. FUNCTION TABLE (each buffer) INPUTS OUTPUT Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2003, Texas Instruments Incorporated 1 SN74AHCT126ĆEP QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCLS551 - DECEMBER 2003 logic diagram (positive logic) 1 1OE 2 1A 3 1Y 4 2OE 5 2A 6...