SN74AHCT126-Q1 Datasheet | Texas Instruments

ures - AEC-Q100 qualified for automotive applications: - Device temperature grade 1: -40°C to +125°C - Device HBM ESD classification level 2 - Device CDM ESD classification level C4B - Available in wettable flank QFN (WBQA) package - Operating range of 4.5 V to 5.5 V - ±8-m A output drive at 5 V - Inputs are TTL-voltage patible - Latch-up performance exceeds 250 m A per JESD 17 2 Applications - Enable or disable a digital signal - Controlling an indicator LED - Debounce a switch - Eliminate slow or noisy input signals 3 Description The SN74AHCT126-Q1 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Package Information PART NUMBER PACKAGE PACKAGE SIZE(1) D (SOIC, 14) 8.7 mm × 6 mm SN74AHCT126 PW (TSSOP, 5 mm × 6.4 -Q1 14) mm BQA (WQFN, 3 mm × 2.5 14) mm BODY SIZE (NOM)(1) 8.7 mm × 3.9...