SN74AHCT573-Q1 Datasheet | Texas Instruments

description /ordering information The SN74AHCT573 is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup ponents. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION{ PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 125°C SOIC - DW Tape and reel SN74AHCT573QDWRQ1 AHCT573QQ1 † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://.ti.. ‡ Package drawings, thermal data, and symbolization are available at http://.ti./packaging. FUNCTION TABLE (each latch) INPUTS OE LE OUTPUT Q L HH LLX HXX Q0 Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright ...