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SN74ALS112A - Dual J-K Negative-Edge-Triggered Flip-Flop

Description

These devices contain two independent J-K negative-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

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Full PDF Text Transcription

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SN54ALS112A, SN74ALS112A DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SDAS199A − APRIL 1982 − REVISED DECEMBER 1994 • Fully Buffered to Offer Maximum Isolation From External Disturbance • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS112A TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) 50 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE (TOP VIEW) 1CLK 1 1K 2 1J 3 1PRE 4 1Q 5 1Q 6 2Q 7 GND 8 16 VCC 15 1CLR 14 2CLR 13 2CLK 12 2K 11 2J 10 2PRE 9 2Q description These devices contain two independent J-K negative-edge-triggered flip-flops.
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