SN74ALS373A Datasheet | Texas Instruments

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C - APRIL 1982 - REVISED MARCH 2002 D Eight Latches in a Single Package D 3-State Bus-Driving True Outputs D Full Parallel Access for Loading D Buffered Control Inputs D pnp Inputs Reduce dc Loading on Data Lines description These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54ALS373A, . . . J OR W PACKAGE SN54AS373 . . . J PACKAGE SN74ALS373A, SN74AS373 . . . DW, N, OR NS PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 LE While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. OE VCC SN54ALS373A, SN54AS373 . . . FK PACKAGE (TOP VIEW) 5D 8Q GND 1Q 4Q 1D A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup ponents. 2D 3 2 1 20 19 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15...