SN74ALS561A Datasheet | Texas Instruments

description SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A - DECEMBER 1982 - REVISED JANUARY 1995 SN54ALS561A . . . J PACKAGE SN74ALS561A . . . DW OR N PACKAGE (TOP VIEW) ALOAD 1 CLK 2 A3 B4 C5 D6 ENP 7 ACLR 8 SCLR 9 GND 10 20 VCC 19 RCO 18 CCO 17 OE 16 QA 15 QB 14 QC 13 QD 12 ENT 11 SLOAD These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock. SN54ALS561A . . . FK PACKAGE (TOP VIEW) A CLK ALOAD VCC RCO The clear function is initiated by applying a low level to either asynchronous clear (ACLR) or synchronous clear (SCLR). ACLR (direct clear) overrides all other functions of the device, while SCLR overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD) or by the bination of a low level at synchronous load (SLOAD) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR, ALOAD, SCLR, and SLOAD are all high. SCLR GND SLOAD ENT B C D ENP ACLR 3 2 1 20 19 9 10 11 12 13 QA QB QC A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches monly associated with a ripple-carry output. Cascading is normally acplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very...