SN74ALS563BN Datasheet | Texas Instruments

description /ordering information These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the plements of data (D) inputs. When LE is taken low, the outputs are latched at the inverse of the levels set up at the D inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup ponents. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 8D SN54ALS563B . . . J OR W PACKAGE SN74ALS563B . . . DW, N, OR NS PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54ALS563B . . . FK PACKAGE (TOP VIEW) 1Q 1D 2D 3D 3 2 1 20 19 2Q 4D 5 17 3Q 5D 6 16 4Q 6D 7 15 5Q 7D 8 14 6Q 9 10 11 12 13 8Q 7Q ORDERING INFORMATION PACKAGE† ORDERABLE PART...