Texas Instruments SN74ALS990
The SN74ALS990 is characterized for operation from 0°C to 70°C.| Part No. | SN74ALS990 |
|---|---|
| Datasheet | SN74ALS990 Download |
| Manufacturer |  Texas Instruments |
| Description | 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH |
| Buy | Stock & Price |
SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS027B – APRIL 1984 – REVISED JANUARY 1995
● 3-State I/O-Type Read-Back Inputs
● Bus-Structured Pinout
● True Logic Outputs
● Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs description This 8-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. DW OR N PACKAGE (TOP VIEW) OERB 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE The eight latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. Read back is provided through the output-enable (OERB) input. When OERB is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs.
● 3-State I/O-Type Read-Back Inputs
● Bus-Structured Pinout
● True Logic Outputs
● Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs description This 8-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. DW OR N PACKAGE (TOP VIEW) OERB 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE The eight latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. Read back is provided through the output-enable (OERB) input. When OERB is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs.
