SN74ALS996 Datasheet | Texas Instruments

description These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability. SN54ALS996 . . . JT PACKAGE SN74ALS996 . . . DW OR NT PACKAGE (TOP VIEW) 1D 1 2D 2 3D 3 4D 4 5D 5 6D 6 7D 7 8D 8 EN 9 RD 10 CLK 11 GND 12 24 VCC 23 1Q 22 2Q 21 3Q 20 4Q 19 5Q 18 6Q 17 7Q 16 8Q 15 OE 14 T/C 13 CLR The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable (EN) input is low. Data can be read back onto the data inputs by taking the read (RD) input low, in addition to having EN low. When EN is high, both the read-back and write modes are disabled. Transitions on EN should only be made with CLK high to prevent false clocking. The polarity of the Q outputs can be controlled by the polarity (T/C) input. When T/C is high, Q is the same as is stored in the flip-flops. When T/C is low, the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable (OE) input high. OE does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off. A low level at the clear (CLR) input resets the internal registers low. The clear function is asynchronous and overrides all other register functions. SN54ALS996 . . . FK PACKAGE (TOP VIEW) 2Q 1Q 1D 2D 3D 4 3 2 1 28 27 26 4D 5 25 3Q 5D 6 24 4Q 6D 7 23 5Q NC 8 22 NC 7D 9 21 6Q 8D 10 20 7Q EN 11 19 8Q 12 13 14 15 16 17...