SN74ALVCH16524 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family - UBT™ Transceiver bines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode - Operates From 1.65 V to 3.6 V - Max tpd of 3.2 ns at 3.3 V - ±24-m A Output Drive at 3.3 V - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - Latch-Up Performance Exceeds 250 m A Per JESD 17 - ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) DESCRIPTION /ORDERING INFORMATION This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK. SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080E - JULY 1996 - REVISED OCTOBER 2004 DGG OR DL PACKAGE (TOP VIEW) GND 1 OEAB 2 A1 3 GND 4 A2 5 A3 6 VCC 7 A4 8 A5 9 A6 10 GND 11 A7 12 A8 13 A9 14 A10 15 A11 16 A12 17 GND 18 A13 19 A14 20 A15 21 VCC 22 A16 23 A17 24 GND 25 A18 26 OEBA 27 CLKENBA 28 56 GND 55 SEL 54 B1 53 GND 52 B2 51 B3 50 VCC 49 B4 48 B5 47 B6 46 GND 45 B7 44 B8 43 B9 42 B10 41 B11 40 B12 39 GND 38 B13 37 B14 36 B15 35 VCC 34 B16 33 B17 32 GND 31 B18 30 CLK 29 GND To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup...