SN74ALVCH16721 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family - EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Latch-Up Performance Exceeds 250 m A Per JESD 17 - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages DESCRIPTION This 20-bit flip-flop is designed specifically for 1.65-V to 3.6-V VCC operation. The 20 flip-flops of the SN74ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052E - JULY 1995 - REVISED AUGUST 2004 DGG, DGV, OR DL PACKAGE (TOP VIEW) OE 1 Q1 2 Q2 3 GND 4 Q3 5 Q4 6 VCC 7 Q5 8 Q6 9 Q7 10 GND 11 Q8 12 Q9 13 Q10 14 Q11 15 Q12 16 Q13 17 GND 18 Q14 19 Q15 20 Q16 21 VCC 22 Q17 23 Q18 24 GND 25 Q19 26 Q20 27 NC 28 56 CLK 55 D1 54 D2 53 GND 52 D3 51 D4 50 VCC 49 D5 48 D6 47 D7 46 GND 45 D8 44 D9 43 D10 42 D11 41 D12 40 D13 39 GND 38 D14 37 D15 36 D16 35 VCC 34 D17 33 D18 32 GND 31 D19 30 D20 29 CLKEN - No internal connection To ensure the high-impedance state during...