SN74AS573A Datasheet | Texas Instruments

description These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54ALS573C, SN54AS573A . . . J OR W PACKAGE SN74ALS573C, SN74AS573A . . . DW OR N PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54ALS573C, SN54AS573A . . . FK PACKAGE (TOP VIEW) 1Q 1D 2D While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup ponents. 8D 3D 3 2 1 20 19 2Q 4D 5 17 3Q 5D 6 16 4Q 6D 7 15 5Q 7D 8 14 6Q 9 10 11 12 13 8Q 7Q OE does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of - 55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each latch) INPUTS OE...