SN74AUC2G125
FEATURES
- Available in the Texas Instruments Nano Free™ Package
- Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub-1-V Operable
- Max tpd of 1.8 ns at 1.8 V
- Low Power Consumption, 10 μA at 1.8 V
- ±8-m A Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 m A Per
JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
DCT PACKAGE (TOP VIEW)
DCU PACKAGE (TOP VIEW)
YZP PACKAGE (BOTTOM VIEW)
1OE 1A 2Y
1 2 3
8 VCC 7 2OE 6 1Y
1OE 1A 2Y
1 2 3 4
8 VCC 7 2OE 6 1Y
5 2A
GND 4 5 2A 2Y 3 6 1Y 1A 2 7 2OE
1OE 1 8 VCC
5 2A
See mechanical drawings for dimensions.
DESCRIPTION
/ORDERING INFORMATION
This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC2G125 features dual line drivers with...
