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SN74AUC2G125 - DUAL BUS BUFFER GATE

Description

This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

Features

  • Available in the Texas Instruments NanoFree™ Package.
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation.
  • Ioff Supports Partial-Power-Down Mode Operation.
  • Sub-1-V Operable.
  • Max tpd of 1.8 ns at 1.8 V.
  • Low Power Consumption, 10 μA at 1.8 V.
  • ±8-mA Output Drive at 1.8 V.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Protection Exceeds JESD 22.
  • 200.

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Datasheet preview – SN74AUC2G125

Datasheet Details

Part number SN74AUC2G125
Manufacturer Texas Instruments
File Size 0.97 MB
Description DUAL BUS BUFFER GATE
Datasheet download datasheet SN74AUC2G125 Datasheet
Additional preview pages of the SN74AUC2G125 datasheet.

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Full PDF Text Transcription

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www.ti.com SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES532D – DECEMBER 2003 – REVISED AUGUST 2007 FEATURES • Available in the Texas Instruments NanoFree™ Package • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 1.8 ns at 1.8 V • Low Power Consumption, 10 μA at 1.8 V • ±8-mA Output Drive at 1.
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