Dual J-k Positive-edge-triggered Flip-flop
| Part number | SN74F109 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 586.73 KB |
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP |
| Datasheet | SN74F109-etcTI.pdf |
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These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse.
See all Texas Instruments datasheets
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