Dual Negative-edge-triggered J-k Flip-flop
| Part number | SN74F112 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 666.05 KB |
| Description | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP |
| Datasheet | SN74F112-etcTI.pdf |
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The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse.
See all Texas Instruments datasheets
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|---|---|
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