SN74HC166A-EP Overview
Key Specifications
Output Type (varies by manufacturer): CMOS
Key Features
- gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input
- The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input
- When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse
- When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse
- During parallel loading, serial data flow is inhibited
