SN74HC166A-Q1 Datasheet | Texas Instruments

n/ordering information This parallel-in or serial-in, serial-out register Features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GND 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CLR serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is acplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on mand with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero. ORDERING INFORMATION{ PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 85°C SOIC - D TSSOP - PW Tape and reel Tape and reel SN74HC166AIDRQ1 SN74HC166AIPWRQ1 HC166AI HC166AI † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://.ti.. ‡ Package drawings, thermal data, and symbolization are available at http://.ti./packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production...