SN74HC273-Q1 Description
/ordering information 3Q 6 3D 7 15 6Q 14 6D This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup 4D 8 4Q 9 GND 10 13 5D 12 5Q 11 CLK time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the...