SN74HC74-EP Datasheet | Texas Instruments

.ti. SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS710 - MARCH 2008 Features - Controlled Baseline - One Assembly Site - One Test Site - One Fabrication Site - Extended Temperature Performance of - 55°C to 125°C - Enhanced Diminishing Manufacturing Sources (DMS) Support - Enhanced Product-Change Notification - Qualification Pedigree (1) (1) ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. - Wide Operating Voltage Range of 2 V to 6 V - Outputs Can Drive up to 10 LSTTL Loads - Low Power Consumption, 80 µA Max ICC - Typical tpd = 15 ns - ±4 m A Output Drive at 5 V - Low Input Current of 1 m A Max DESCRIPTION/ORDERING INFORMATION The SN74HC74 device contains two independent D-type positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs. - 55°C to 125°C SOIC - D TSSOP - PW ORDERING INFORMATION(1) PACKAGE...